How to Convince Xilinx Not to Optimize Away Your Wires!

As I was writing my last post, I remembered how much trouble my lab partner and I had with Xilinx WebPack 9.2 optimizing away our clock wire during synthesis, along with everything that was attached to (read: everything important). After several hours of fruitless Google searching, I finally came across a tiny blurb in a Xilinx PDF saying that putting

/* syn_keep = 1 */

next to a wire will force it to survive optimization!

I'm not sure about the specifics, but I do know is that it saved our project at the last minute, and it very may well save yours too!

Keep in mind, however, that more than likely there's a reason that Xilinx wants to kill your wires. You probably have other problems somewhere in your code (did you check for latches?). Also, keep in mind that this comment must be put next to each wire that you want to survive, not just at the end of a long declaration with many wires.

Happy coding!

Building a MIPS processor

To anyone who wishes to build a simple single-cycle MIPS processor, here's a diagram of how to do so!

Please excuse the not-so-straight lines, this was a crappy scan of a 22"x25.5" hand drawn diagram. It was made for a processor design class that I just finished up, and can execute the following instructions:

• add
• addi
• sub
• mul
• lw
• sw
• sb
• lh
• lb
• sh
• lui
• and
• or
• nor
• xor
• andi
• ori
• xori
• sll
• srl
• slt
• slti
• movn
• bgez
• beq
• bne
• bgtz
• blez
• bltz
• j
• jr
• jal

I don't know if anyone will ever have a use for this, but here it is, for all the world to enjoy! So.... Enjoy! :)